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lt4351 1 4351fb typical application description mosfet diode-or controller the lt ? 4351 creates a near ideal diode using external single or back-to-back n-channel mosfets. this ideal diode function permits low loss oring of multiple power sources. power sources can easily be ored together to increase total system power and reliability with minimal effect on supply voltage or ef? ciency. disparate power supplies can be ef? ciently ored together. the ic monitors the input supply with respect to the load and turns on the mosfet(s) when the input supply is higher. if the mosfets r ds(on) is suf? ciently small, the lt4351 will regulate the voltage across the mosfet(s) to 15mv. a status pin indicates the mosfet on-state. an internal boost regulator generates the mosfet gate drive voltage. low operating voltage allows for oring of supplies as low as 1.2v. the lt4351 will disable power passage during undervolt- age or overvoltage conditions. these voltages are set by resistive dividers on the uv and ov pins. the undervoltage threshold has user programmable hysteresis. overvoltage detection is ? ltered to reduce false triggering. the lt4351 is available in a 10-pin msop package. dual 5v redundant supply features applications n low loss replacement for oring diode in multiple sourced power supplies n external n-channel mosfets for high current capability n internal boost regulator supply for mosfet gate drive n wide input range: 1.2v to 18v n fast switching mosfet gate control n input under and overvoltage detection n status and fault outputs for monitoring n internal mosfet gate clamp n available in a 10-pin msop package n paralleled power supplies n uninterrupted supplies n high availability systems n n + 1 redundant power supplies l , lt, ltc, ltm, linear technology and the linear logo are registered trademarks of linear technology corporation. all other trademarks are the property of their respective owners. load c load gate out v in v dd sw lt4351 uv ov status 1 f 24.9k 1% 232 1% 1.47k 1% 10 f 5v power supply 1 4.7 h mbr0530 mbr0530 fault gnd si4862dy si4862dy 1 s 1 s gate out 5v common v in v dd sw lt4351 uv ov 4351 ta01 gnd power supply 2 1 f 24.9k 1% 232 1% 1.47k 1% 10 f 5v 4.7 h mbr0530 mbr0530 status fault
lt4351 2 4351fb pin configuration absolute maximum ratings v in voltage ................................................ C0.3v to 19v out voltage ............................................. C0.3v to 19v v dd voltage .............................................. C0.3v to 30v fault , status voltages .......................... C0.3v to 30v fault , status current .......................................... 8ma uv, ov voltages ......................................... C0.3v to 9v sw voltage .............................................. C0.3v to 32v operating temperature range lt4351c .................................................. 0c to 70c lt4351i ............................................... C40c to 85c junction temperature (note 2) ............................ 125c storage temperature range .................. C65c to 150c lead temperature (soldering, 10 sec) .................. 300c (note 1) 1 2 3 4 5 gate v dd v in sw gnd 10 9 8 7 6 out status fault uv ov top view ms package 10-lead plastic msop t jmax = 125c, ja = 120c/w order information lead free finish tape and reel part marking package description temperature range lt4351cms#pbf lt4351cms#trpbf ltzz 10-lead plastic msop 0c to 70c lt4351ims#pbf lt4351ims#trpbf lta1 10-lead plastic msop C40c to 85c consult ltc marketing for parts speci? ed with wider operating temperature ranges. consult ltc marketing for information on non-standard lead based ? nish parts. for more information on lead free part marking, go to: http://www.linear.com/leadfree/ for more information on tape and reel speci? cations, go to: http://www.linear.com/tapeandreel/ electrical characteristics symbol parameter conditions min typ max units supply and protection v in operating range l 1.2 18 v i vin v in supply current v in = 1.2v, v out = 1.1v, v dd = 12.3v v in = 18v, v out = 17.9v, v dd = 29.1v l l 1.41 1.71 2 2.1 ma ma v uv(th) undervoltage turn-off voltage threshold uv falling l 290 300 310 mv i uv(hyst) i uv hysteresis difference between i uv at v uv(th) + 10mv and v uv(th) C 10mv l 71013 a i uv uv input bias current v uv = v uv(th) + 10mv l C100 C400 na v ov(th) overvoltage threshold ov rising l 290 300 310 mv the l denotes the speci? cations which apply over the full operating temperature range, otherwise speci? cations are at t a = 25c. v in = v out = 5v, v dd = 16.1v, v uv = 0.4v, v ov = 0.2v, gate open, unless otherwise speci? ed.
lt4351 3 4351fb note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. electrical characteristics the l denotes the speci? cations which apply over the full operating temperature range, otherwise speci? cations are at t a = 25c. v in = v out = 5v, v dd = 16.1v, v uv = 0.4v, v ov = 0.2v, gate open, unless otherwise speci? ed. symbol parameter conditions min typ max units i ov ov input bias current v ov = v ov(th) C 10mv l C100 C400 v v f(on) fault pin on-voltage i f = 5ma in fault condition l 0.14 0.25 v i f(off) fault pin leakage current v f = 30v, v in = 4.9v l 0.04 1 a boost supply v br boost regulation trip voltage measured as v dd to v in , rising edge l 10.2 10.7 11.1 v t off boost supply off-time 600 ns i swlim boost supply switch current limit l 350 450 650 ma gate drive v ior input-to-output regulated voltage l 41525 mv v gl gate voltage limit v in = 5v, v out = 4.9v, v dd = 13v measured with respect to v dd l C2.3 C3 v v g(max) maximum gate voltage v in = 5v, v out = 4.9v, v dd = 16.1v measured with respect to v out l 7 7.4 7.8 v v g(off) gate off-voltage v out = 5.1v l 0.16 0.30 v i gso gate source current v out = 4.9v, v gate = 9v 0.670 a i gsk gate sink current v out = 5.1v, v gate = 9v 0.670 a v dd operating range l 30 v i vdd v dd supply current v in = 1.2v, v out = 1.1v, v dd = 12.3v, gate open v in = 18v, v out = 17.9v, v dd = 29.1v, gate open l l 3 3.6 4 5.6 ma ma status functions v gis minimum gate voltage for turning on status v out = 4.9v, i status = 1ma l 0.75 1 v v iogf v in to v out fault voltage with open gate v out falling, measured with respect to v in 185 210 230 mv v st(on) status pin on-voltage i st = 5ma, v out = 4.9v, status on l 0.13 0.25 v i st(off) status pin leakage current v st = 30v, status off, v in = 4.9v l 0.04 1 a note 2: t j is calculated from the ambient temperature t a and power dissipation p d according to the following formula: t j = t a + (p d ? 120c/w)
lt4351 4 4351fb typical performance characteristics overvoltage threshold vs v in overvoltage hysteresis vs temperature overvoltage turn-off delay vs overvoltage overdrive undervoltage threshold vs temperature overvoltage threshold vs temperature undervoltage threshold vs v in t a = 25c, unless otherwise noted. i vin vs temperature i vdd vs temperature gate off-voltage vs temperature temperature (c) C50 290 v uv(th) (mv) 292 296 298 300 310 304 0 50 75 4351 g01 294 306 308 302 C25 25 100 125 v in = 1.2v v in = 5v v in = 12v v in = 20v temperature (c) C50 293 v ov(th) (mv) 297 299 305 0 50 75 4351 g02 295 301 303 C25 25 100 125 v in = 1.2v v in = 5v v in = 12v v in = 20v v in (v) 0 v uv(th) (mv) 302 306 310 16 4351 g03 298 294 300 304 308 296 292 290 4 2 8 6 12 14 18 10 20 v in (v) 0 v uv(th) (mv) 302 306 310 16 4351 g04 298 294 300 304 308 296 292 290 4 2 8 6 12 14 18 10 20 temperature (c) C50 C25 0 ov hysteresis (mv) 10 25 0 50 75 4351 g05 5 20 15 25 100 125 v in = 5v ov voltage above threshold (mv) 0 0 turn-off delay (s) 2 6 8 10 20 14 10 20 25 3451 g06 4 16 18 12 5 15 30 35 v in = 5v temperature (c) C50 1.0 i vin (ma) 1.1 1.3 1.4 1.5 2.0 1.7 0 50 75 4351 g07 1.2 1.8 1.9 1.6 C25 25 100 125 v in = 1.2v v in = 5v v in = 12v v in = 20v temperature (c) C50 2.0 i vdd (ma) 3.0 3.5 4.5 0 50 75 4351 g08 2.5 4.0 C25 25 100 125 v in = 1.2v v in = 5v v in = 12v v in = 20v temperature (c) C50 0 v goff (v) 0.05 0.15 0.20 0.25 0.50 0.35 0 50 75 4351 g09 0.10 0.40 0.45 0.30 C25 25 100 125 v in = 5v v out = 5v v in = 5v v out = 5.1v
lt4351 5 4351fb typical performance characteristics gate pin turn on and off waveform with 10nf capacitor load typical sw pin waveform typical sw pin waveform sw pin waveform at maximum boost regulator output t a = 25c, unless otherwise noted. 50ns/div v gate 2v/div v in = 5v v out = 4.9v to 5.1v square wave 4351 g10 turn on turn off 500ns/div v sw 5v/div v in = 5v l = 4.7h 4351 g11 10s/div v sw 5v/div v in = 5v 4.7h inductor 4351 g12 10s/div v sw 5v/div v in = 5v 4.7h inductor 4351 g13
lt4351 6 4351fb pin functions gate (pin 1): mosfet gate drive pin. this pin is tied to the gate(s) of the external n-channel mosfet(s). the gate pin drives high when uv is above the v uv(th) threshold, ov is below the v ov(th) threshold and v in is greater than out by 15mv. when not driven high, gate actively pulls to gnd. gate can sink or source up to 600ma. v dd (pin 2): gate drive supply pin. this is the supply pin for the gate drive ampli? er. it is either generated by the onboard boost regulator or supplied externally. when turning on the mosfet(s), a large high current pulse ? ows through this pin. bypass the pin with a 1f capaci- tor placed in close proximity to the part. the voltage on this pin is also the feedback for the boost regulator. if the v dd voltage exceeds the v in voltage by 10.7v, the boost switch is held off. v in (pin 3): input supply pin. this pin is the supply pin for the control circuitry and the boost regulator. it is also one input in conjunction with out for controlling the mosfet(s). bypassing should include a low esr/esl capacitor placed in close proximity to the part. sw (pin 4): boost regulator switch pin. this pin is the boost regulator switch output. it is connected to the boost inductor and the boost diode. peak switch current is limited internally to 450ma. a schottky diode between gnd and sw is required. if an external v dd supply is used, leave this pin open. gnd (pin 5): device ground pin. this pin is ground for the boost switch, gate driver as well as the control circuitry. tie the v in and v dd bypass capacitors and ground plane close to this pin to minimize the effects of switching cur- rents on part performance. ov (pin 6): overvoltage shutdown pin. this pin is used for input overvoltage detection. it is connected to a resis- tive divider from v in . when the voltage exceeds the ov threshold (0.3v), gate is pulled to gnd disabling power transfer. in addition, the fault pin pulls low indicating a fault. overvoltage detection has ? ltering on it to prevent false triggering. the ? ltering depends on the level of over- drive. filtered tripping will occur when ov exceeds 0.3v. if ov exceeds 0.33v, the gate immediately turns off (no ? ltering). if overvoltage detection is not required, ground the ov pin. see the applications information section for further information. uv (pin 7): undervoltage shutdown pin. this pin is used for the undervoltage detect function. it is connected to a resistive divider from v in . when the voltage is below the uv threshold, gate pulls to gnd disabling power transfer. in addition, the fault pin pulls low indicating a fault. when the uv pin voltage drops below the threshold, a 10a current is pulled from the divider to provide hys- teresis. if undervoltage detection is not required, tie the uv pin to a voltage greater than 320mv and not greater than v in . do not force more than 9v on uv due to an internal clamp. see the applications information section for further information. fault (pin 8): fault comparator status pin. this pin pulls low when a fault occurs. a fault has occurred if the uv pin is below threshold or the ov pin is above threshold. the fault pin low indicates that there is a problem with the v in (source) supply. gate is pulled to gnd during a fault, disabling the mosfet(s) and prohibits common supply contamination. if the gate pin goes to compliance (gate equals the lesser of v dd C 2.3v or out + 7.4v) and v in is greater than out by more than 0.21v, fault turns on as an indicator that the mosfets are probably not function- ing. leave this pin open if not used. status (pin 9): mosfet status pin. this pin pulls low when gate is above v in by more than 0.7v and v in is greater than out by 15mv. this indicates the mosfet is on. leave this pin open if not used. out (pin 10): common supply pin. this pin is connected to the supply common and is used in conjunction with v in as one input controlling the mosfet(s).
lt4351 7 4351fb block diagram + C 15mv enable enable qsw c uv c ov 0.3v 0.3v 0.33v c ovf gnd ov uv r2 r1 r a sw v dd v in gate v in C + C + 3 2 4 6 5 7 open mosfet detect 600ns one shot C + 1 10 9 8 10.7v reg C + C + r b C + C + v in from individual supply to common supply v out out out st status fault 4351 bd driver
lt4351 8 4351fb operation increasingly, system designers have to deal with multiple supply sources. the multiplicity may provide parallel, redundant supplies for increased reliability or provide a means of connecting disparate supplies. in all cases the desire is for behavior like a diode but with no loss or voltage drop. oring diodes have been the conventional means of con- necting these supplies. the disadvantage of this approach is that diodes introduce ef? ciency loss because of their forward voltage drop. this variable voltage drop also de- generates supply tolerance. additionally, diodes provide no information concerning the status of the sourcing supply. separate control must also be added to ensure that a supply that is out of range is not allowed to affect the common supply. the lt4351 eliminates these problems by using n-channel mosfets as the pass elements. the mosfet is turned on when power is being passed, allowing for a low voltage drop from the supply to the load. when the input source voltage drops below the output common supply voltage it turns off the mosfet, thereby matching the function and performance of an ideal diode. the lt4351 drives either a single mosfet or dual back- to-back mosfets. dual mosfets are chosen to eliminate current ? ow from the input supply to the output supply when the v in voltage is greater than out. a driver ampli? er monitors the input (v in ) and output (out) and controls the mosfets. if v in exceeds out by 15mv, gate goes high and turns on the mosfet(s) allowing for power passage. undervoltage and overvoltage comparators c uv , c ov and c ovf also control power passage. a resistive divider in conjunction with the uv and ov pins sets appropriate thresholds such that the mosfet(s) is off when the uv pin is below 300mv or ov pin is above 300mv. to help deal with the transients on the supply lines, the uv input has current hysteresis. when the uv voltage drops below the 300mv threshold, a 10a current is pulled from the pin. thus the user can set the hysteresis level through appropriate values in the divider. overvoltage shutdown occurs in two stages. the ? rst oc- curs when the ov pin exceeds the 300mv reference. when ov just exceeds the reference, an internal capacitor starts charging, delaying the signal to turn off the mosfet(s). the second occurs when the ov pin exceeds 330mv. the ovf comparator will immediately trip pulling gate to gnd. this affords a delay inversely proportional to the amount of overdrive. this also provides for glitch immunity without compromising response time in the event of a serious overvoltage condition. the fault output indicates the status of the c ov , c ovf and c uv comparators. it pulls low during a fault condi- tion. it also pulls low when gate is at compliance and v in > out by more than 0.21v indicating a probable nonfunctioning mosfet. compliance occurs when gate is at the lesser of out + 7.4v or v dd C 2.3v. fault derives its drive from the greater of v in or out. it is active if v in or out is greater than 0.9v. if v in or out is below this level, the output state is not guaranteed. the gate drive consists of a high current, wide bandwidth ampli? er (driver). when the ampli? er is enabled, it attempts to regulate the gate voltage such that the voltage across the mosfet(s) is approximately 15mv. if the mosfet(s) on resistance is so high as to prevent regulation, then gate goes to compliance and the mosfet(s) fully turns on. the inputs to the ampli? er are v in and out. the gate pin sources current from v dd and sinks current to gnd. the maximum gate to v in voltage is the lesser of v dd C 2.3v or 7.4v above v out or v in (internal clamp voltage). the status comparator, st, pulls low when gate ex- ceeds v in by 0.7v. this occurs when v in > out + 15mv. the status pin pulls low as an indication that power is passing through the mosfet(s). if v in is greater than out by 0.21v and gate > v in + 7.4v or at compliance (gate = v dd C 2.3v), status will go high as an indication of a likely open mosfet. fault will pull low in this state indicating the probable fault. the gate drive ampli? er and status function derive power from v dd . the circuit requires v dd > 2.5v. if v dd is present, the gate drive ampli? er and status are active independent of the state of v in . if in a fault, gate pulls actively low. in the event of v dd collapse there still is an active pull-down (though of lesser strength) of gate powered from out, guaranteeing turn off.
lt4351 9 4351fb setting fault thresholds the gate drive ampli? er implements the ideal diode func- tion. the fault comparators (uv and ov) prevent out of range input voltages from affecting the output by disabling the ampli? er during these conditions. think of the uv and ov as gating the ideal diode function, something a regular diode cannot do. a resistive divider from v in to uv and one from v in to ov are the usual way of setting the fault thresholds. for uv the resistor values are set by: r uv i r v uv v r hyst uvhyst uv fault uv 2 12 = = ? ? where uv hyst is the desired undervoltage hysteresis at the input. uv fault is the desired undervoltage trip volt- applications information figure 1 age at the input. v uv is the part undervoltage trip point (0.3v) and i hystuv is the undervoltage hysteresis current (10a). see figure 1. the divider on the ov pin is a straightforward resistive divider (figure 2): r ov v r r v rrdividerc b fault ov a a ab = ? ? ? ? ? ? = ? . , 1 03 u urre n where ov fault is the desired overvoltage trip point at the input and v ov is the ov pin threshold (0.3v). the ov pin has 7mv of voltage hysteresis at room. it is possible to do both dividers together using only three resistors though with more interdependence in compo- nents (figure 3). the input bias current for uv and ov is less than 200na, so keep resistor values less than 10k. the on-chip boost regulator uses a constant off-time control scheme. when v dd is below the regulation trip voltage, the switch turns on after a 600ns off-time. when the switch turns on current ramps up in the inductor until the current limit is reached (450ma). the switch turns off and the inductors current ? ows through the external diode to charge up the v dd capacitor. if v dd is still too low, the switch turns on again after a ? xed off-time of 600ns. operation the boost regulator regulates v dd to approximately 10.7v above v in when v dd is above this level, the sw transistor turn-on is disabled. when v dd falls below this level by the hysteresis level, the sw transistor is allowed to turn on. there is approximately 0.15v of hysteresis. figure 2 figure 3 figure 4 r2 r1 uv i hys 10a v uv 300mv v in uv turning on uv turning off r2 r1 uv i hys 10a v uv 300mv 4351 f01 v in r b r a ov v ov 300mv 4351 f02 v in r2 r3 r1 ov uv 4351 f03 v in c1 r2a r2b r1 uv 4351 f04 v in
lt4351 10 4351fb in that case, the resistor values are set by: r uv i r v uv ov v uv v r r vuv ov uv v r hyst uvhyst uv fault fault ov fault uv ov fault fault fault uv 3 23 13 = = = () ?? ? ? ? ?? ? hysteresis helps prevent erratic behavior due to the noise on v in . two of the most common noise sources are: v in dipping when the mosfets ? rst turn on and draw down the voltage on the v in capacitors, and the boost regulator switch turning on and drawing current from the v in capaci- tors. use low esr capacitors for v in and out ? ltering. note that because the uv pin uses current hysteresis, placing a capacitor on uv to ground to ? lter noise will reduce the effective hysteresis. filtering can be achieved by splitting the r2 resistor, as shown in figure 4. to defeat undervoltage fault detection, the uv pin should be tied higher than 0.33v. uv can be tied to v in provided v in < 9v. overvoltage fault detection can be defeated by grounding the ov pin. do not exceed v in . applications information external shutdown to externally turn off the mosfets, such as to disable the supply, use an open-collector transistor pulling down on the uv pin. note this will not turn off the boost regulator which will continue to operate. boost regulator the boost regulator will start working as soon as v in is greater than 0.85v. the regulator will supply all the cur- rent for the gate drive ampli? er. while the ampli? er itself requires only about 3ma, larger current pulses are required when charging the mosfet gate. the reservoir capacitor on v dd will provide this current (figure 6). the regulator performance is relatively insensitive to the inductor value. the inductor value does control the fre- quency of operation. a 4.7h inductor is recommended for v in voltages less than 10v and 10h for v in voltages greater than 10v. several inductors that work well with the lt4351 are listed in table 1. many different sizes and shapes are available. consult each manufacturer for more detailed information and for their entire selection of related parts. the switching frequency for the boost regulator is around 1mhz so ferrite core inductors should be used to obtain the best ef? ciency. the inductor must handle a peak current of 0.7a minimum and have a dc resistance of 0.5 or less. shielded inductors are recommended to reduce the noise due to inductive switching. table 1. recommended inductors part number ind (h) dcr (m) vendor lps3314-472ml lps4012-103ml 4.7 10 175 350 coilcraft 847-639-6400 www.coilcraft.com 744029004 744042100 4.7 10 200 150 wrth elektronik www.we-online.com sd3112-4r7-r sd3118-100-r 4.7 10 246 295 coiltronics www.coiltronics.com l1 d1 d2 qsw gnd sw v dd c dd 4351 f06 v in lt4351 figure 5. graphical representation of the uv and ov functions overvoltage filtered fault input referred ov referred uv referred v uv = 0.33v v uv = 0.3v v uv < 0.3v v ov > 0.3v v ov = 0.3v 4351 f05 ov fault uv fault + uv hyst uv fault undervoltage hysteresis overvoltage fault: gate low undervoltage fault: gate low gate controlled by v in C v out figure 6
lt4351 11 4351fb for v in less than 2v, choose a dc resistance less than 0.2. note that v dd current referred to the input supply is higher. a ? rst order approximation of the input current is: i v i vinvdd in vdd =+ ? ? ? ? ? ? 1 10 6 80 . ? % under normal operation, the v dd current is under 10ma and the boost regulator operates in burst mode ? operation. if any additional load is added, ensure that the regulator is capable of supplying that load. as the load is increased, the boost regulator will switch into continuous mode op- eration. further increases in load will collapse the boost regulator voltage. operating the regulator with increased load will cause increased ic power dissipation and temperature, which must be taken into consideration. a 100ns delay from detecting the switch current limit to turning off the power switch produces an overshoot of the inductor current from the 0.45a switch limit. the amount of overshoot depends on the boost regulator inductance. choosing an inductor that can handle 0.75a peak current will be suf? cient for the recommended inductors. diode selection schottky diodes, with their low forward voltage drop and fast switching speed, are the best match for the lt4351 boost regulator. select a diode that can handle 0.75a peak current and a reverse breakdown of 15v greater than the maximum v in . applications information v dd capacitor selection low esr (equivalent series resistance) capacitors should be used on v dd to minimize the output ripple voltage. multilayer ceramic capacitors are the best choice, as they have a very low esr and are available in very small packages. always use a capacitor with a voltage rating at least 12v greater than v in . capacitors two types of input capacitors are generally needed for the lt4351. the ? rst is a large bulk capacitor that takes care of ringing associated with inductance of the input supply lines and provides charge for the load when switching the mosfet. the input parasitic inductance in conjunction with c b and its esr create an lcr network. the input lcr can be stimulated by the boost regulator switch current or load current transients when the mosfets are on. to reduce ringing associated with input inductance, c b should be: c l r b in esr 4 2 ? where c b is the capacitor value, r esr is the capacitors esr and l in is the inductance of the input lines. while damped ringing is not necessarily bad, it may pro- duce unexpected results as the lt4351 ideal diode reacts to the varying v in to out voltage. typically an electrolytic or tantalum low esr capacitor would be used. figure 7a illustrates v in for a low value of c b and figure 7b shows it with a correctly sized value. figure 7a. example of input voltage ringing with low c in capacitor at mosfet turn off figure 7b. example of input voltage with suf? cient c in capacitor at mosfet turn off 10s/div v in 200mv 4351 f07a 10s/div v in 200mv 4351 f07b burst mode is a registered trademark of linear technology corporation
lt4351 12 4351fb applications information as an example, for 500nh of inductance and r esr of about 100m, then: c nf f = 4 500 01 200 2 ? . check vendor data for esr and iterate to get the best value. additional c b capacitance may be required for load concerns. if the boost regulator is being used, place a 10f low esr ceramic capacitor from v in to gnd. place a 10f and a 0.1f ceramic capacitor close to v in and gnd. these capacitors should have low esr (less than 10m for the 10f and 40m for the 0.1f). these capacitors help to eliminate problems associated with noise produced by the boost regulator. they are decoupled from the v in supply by a small 1 resistor, as shown in figure 8. the lt4351 will perform better with a small ceramic capacitor (10f) on out to gnd. external boost supply the v dd pin may be powered by an external supply. in this case, simply omit the boost regulator inductor and diode and leave the sw pin open. suitable v dd capacitance (minimum of a 1f ceramic) should remain due to the current pulses required for the gate driver. the v dd current consists of 3.5ma of dc current with the current required to charge the mosfets gate which is dependent on the gate charge required and frequency of switching. typically the average current will be under 10ma. mosfet selection the lt4351 uses either a single n-channel mosfet or back-to-back n-channel mosfets as the pass element. back-to-back mosfets prevent the mosfet body diode from passing current. use a single mosfet if current ? ow is allowable from input to output when the input supply is above the output (limited overvoltage protection). in this case the mosfet should have a source on the input side so the body diode conducts current to the load. back-to-back mosfets are normally connected with their sources tied together to provide added protection against exceeding maximum gate to source voltage. selection of mosfets should be based on r ds(on) , bv dss and bv gss . bv dss should be high enough to prevent breakdown when v in or out are at their maximum value. r ds(on) should be selected to keep within the mosfet power rating at the maximum load current (i 2 ? r ds(on) ) bv gss should be at least 8v. the lt4351 will clamp the gate to 7.5v above the lesser of v in or out. for back- to-back mosfets where sources are tied together, this allows the use of mosfets with a vgs max rating of 8v or more. if a single mosfet is used, care must be taken to ensure the vgs max rating is not exceeded. when the mosfet is turned off, the gate voltage is near ground, the source at v in . thus, mosfet vgs max must be greater than v in(max) . if a single mosfet is used with source to v in , then bv gss should be greater than the maximum v in since the mosfet gate is at 0.2v when off. figure 8. v in capacitors v in 1 7 c v3 10f c v1 10f c b l in parasitic c v2 0.1f v in gate lt4351 4351 f08 gnd
lt4351 13 4351fb applications information the gate drive ampli? er will attempt to regulate the volt- age across the mosfets to 15mv. regulation will be achieved if: r mv i for two mosfets and r mv i ds load ds loa < < 15 2 15 ? d d for a gle mosfet sin this requires very low r ds values. this may be achieved by paralleling mosfets, but be careful to keep interconnection trace resistance low. in the event that regulation cannot be achieved, the gate drive ampli? er will drive gate to its clamp and achieve the best r ds possible at that level. status the status pin sinks current when the input (v in ) is above output (out) by 15mv and gate is above v in by 0.7v. this will normally indicate that power is being passed though the mosfets. in the event of a nonfunctional mosfet, the gate voltage will be driven high (to the gate clamp voltage). if v in is greater than out by more than 0.21v, the fault pin will sink current to signal the potential problem. there is no direct measurement or con? rmation of cur- rent ? owing in the mosfets. current is shared between sources based on their voltage and series resistance. if precision load sharing is desired, the ltc4350 may be a more suitable part. redundant supplies the lt4351 is an improved solution for oring redundant supplies because of its lower forward drop versus con- ventional diodes. the lower forward drop signi? cantly improves overall ef? ciency, improves the voltage tolerance at the load and provides for a more accurate transition from supply to supply and more accurate load sharing between supplies. oring can be done either at the load or at the source. figure 9 shows some examples. oring at the load is usually the safest method since it protects against shorts in interconnects. the lt4351 tighter forward-voltage tolerance makes it easier to balance current between similar supplies using the droop method. the droop method uses the supply voltage and series resistance in the power path to provide load sharing. in this case, size the mosfets r ds(on) low to allow for regulation. lt4351 board lt4351 load source 1 backplane source 2 lt4351 board lt4351 load 4351 f09 source 1 backplane source 2 figure 9. redundant backplane supplies
lt4351 14 4351fb applications information oring disparate supplies the lt4351 provides an easy solution for connecting together different types of power sources. again, because of the low forward drop, the ef? ciency of the system is improved and the voltage transition between supplies is more accurate. in addition, the undervoltage and overvolt- age features of the lt4351 provide options for enabling and disabling the supplies that are not available from a common diode. figure 10 shows some examples of con- necting disparate supplies. start-up considerations there is no inherent shutdown in the part. as v in ramps up, the boost regulator starts at about 0.85v and becomes fully operational by 1.1v. the undervoltage and overvolt- age comparators become accurate by 1.2v. the gate drive ampli? er keeps gate low during this period with either a passive pull-down, a weak active pull-down if out is greater than 0.8v or with the full gate drive sink if v dd is above 2.2v. once v in is greater than 1.2v and v dd is up, the part then operates normally. the uv and ov pins will control the enabling of the gate driver and once enabled, the v in to out voltage controls mosfet turn on. if v dd is still being charged when the gate driver turns on the mosfet, the gate pin tracks with the v dd in- crease until it reaches either the gate clamp voltage or the compliance of the gate driver. if v dd is present with- out v in or out, the gate pin actively sinks low. lt4351 isolated system supply from wall adapter isolated battery backup three source oring provides protection against out of range supplies wall adapter system supply load lt4351 battery wall adapter load + lt4351 battery lt4351 lt4351 wall adapter load 4351 f10 + system supply figure 10
lt4351 15 4351fb applications information power dissipation the internal power dissipation of the lt4351 is comprised of the following four major components: dc power dis- sipation from v in , dc power dissipation from v dd , the dissipation in the boost switch including the base drive, and dynamic power dissipation due to current used to charge and discharge the mosfets. the dc components are: p dcvin = i vin ? v in p dcvdd = i vdd ? v dd figure 11 shows the internal dissipation of the boost regulator as a function of v in and inductor value. figure 11 represents the worst-case condition with the regulator on all the time, which does not occur in normal practice. since the boost regulator supplies current for v dd , the current is the v dd supply current (3.5ma) plus the average current to charge the gate. for a gate charge of 50nc at a 10khz rate, this adds 0.5ma of current. the power dis- sipated by the boost regulator to supply the 4ma is shown in figure 12, representing a more typical situation. finally, the gate driver dissipates power internally when charging and discharging the gate of the mosfets. this power depends on the input capacitance of the mosfets and the frequency of charge and discharge. the power associated with this can be approximated by: pfvq v gate g dd g in = ? ? ? ? ? ? ???? 1 16 figure 11. p boost(max) figure 12. p boost(typ) v in (v) 0 p boost (w) 0.20 0.25 l = 10h l = 4.7h 20 4351 f11 0.15 0.10 5 10 15 0.30 v in (v) 0 p boost (w) 0.015 0.020 l = 4.7h 20 4351 f12 0.010 0.005 5 10 15 0.025
lt4351 16 4351fb where q g is the required gate charge to charge the mos- fet to the clamp voltage (7.4v) and f g is the frequency at which the gate is charged and discharged. normally f g is low and the resulting power would be very low. figure 13 shows p gate for a 50nc gate charge at a 1khz rate. total power dissipation is the sum of all of p dcvin , p dcvdd , p boost and p gate . figure 14 is representative of the total power dissipation of a typical application at steady state. the die junction temperature is then computed as: t j = t a + ja ? p total where t j is the die junction temperature, t a is the ambi- ent temperature, ja is the thermal resistance of the part (120c/w) and p total is ascertained from the above. therefore, a 0.1w power dissipation causes a 12 tem- perature rise above ambient. design example the following demonstrates the calculations involved for setting design components for a 5v system that requires 5a. two supplies are used to do this. the v in supply will be deemed in spec when it is within 5% of nominal. allow 5% of hysteresis for uv. so, uv fault = 4.75v, uv hyst = 0.25v ov fault = 5.5 two separate resistive dividers are used. for the uv divider: r uv i v a kuse k r hyst uvhyst 2 025 10 25 24 9 1 == = () = . . r rv uv v kv vv uv fault uv 2 24 9 0 3 475 03 ? ? .?. .?. = r1 = 1.68k. the closest 1% value is 1.69k the ov resistors are set as a straight resistive divider. if the current in the r a , r b divider is 200a, then: r v ma kuse k then r ov a b fa == = 03 200 15 147 1 . ..(%) u ult ov a v rk ? . . ?. 1 55 03 1147 ? ? ? ? ? ? = ? ? ? ? ? ? r b = 25.48, use 25.5k applications information figure 13. p gate vs v in (v dd = v in + 10.7) v in (v) 0 p gate (w) 0.002 0.003 20 4351 f13 0.001 0 5 10 15 0.004 f gate = 1khz q g = 50nc v in (v) 0 power (w) 0.10 0.12 20 4351 f14 0.08 0.06 5 10 15 0.16 0.14 l = 10h l = 4.7h v dd = v in + 10 0.5ma gate current figure 14. total power (typical)
lt4351 17 4351fb gate out v in uv ov 1 f 10 f mbr0530 mbr0530 r1 1.69k 1% r b 25.5k 1% v in 5v lt4351 sw v dd status 5 fault gnd si4838dy 3 7 6 4 2 110 9 8 r a 1.47k 1% r2 24.9k 1% 1 0.1 f 220 f 10 f 5v 2k 4351 f15 out 2k 10 f 4.7 h figure 15. 5v/5a design example applications information for regulation, the mosfets must have: r mv a m ds <= 15 25 15 ? . this very low value cannot be accomplished with a single set of mosfets so a decision must be made whether to use multiple mosfets or to live with an unregulated off- set. since low m r ds(on) is available, the ir drop using a single mosfet would still be acceptable. for r ds(on) = 4m the drop is 2 ? 5a ? 4m = 40mv. the ? nished schematic is shown in figure 15. layout considerations there are two considerations for board layout. the ? rst is that v in and v dd bypass capacitors should be as close to the part as possible. the gnd pin should represent the common tie point. the resistive dividers for uv and ov should tie here as well. take care that current ? ow to the load (both through v in and gnd), does not inadvertently produce errors due to ir drops in pcb traces. keep the traces to the mosfets wide and short and close to the part. the pcb traces associated with the power path through the mosfets should have low resistance.
lt4351 18 4351fb typical applications lead acid battery backup 5v redundant supply with external v dd gate out v in uv ov 1f r1 1.69k 1% r b 25.5k 1% lt4351 sw v dd status 5 fault gnd 1st source si4838dy 3 1 10f 7 6 4 2 110 9 8 r a 1.47k 1% r2 24.9k 1% 0.1f 100f 10f 10f 2k 4351 f15 2k load 4351 ta03 common 5v source 12v source 2nd 5v source 2nd 12v source 2nd lt4351 circuit + gate out v in uv ov 1f 10f mbr0530 mbr0530 r1 365 7 1% r b 73.2k 1% 10h 12v lead-acid battery charger lt4351 sw v dd status 5 fault gnd si4408dy 3 7 6 4 2 110 9 8 r a 1.5k 1% r2 12.7k 1% 1 7 0.1f 220f 10f 10f 10k 4351ta02 out load 10k uv fault = 10.8v ov fault = 15v 14v power supply + +
lt4351 19 4351fb information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no representa- tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. package description msop (ms) 0307 rev e 0.53 0.152 (.021 .006) seating plane 0.18 (.007) 1.10 (.043) max 0.17 C?0.27 (.007 C .011) typ 0.86 (.034) ref 0.50 (.0197) bsc 12 3 45 4.90 0.152 (.193 .006) 0.497 0.076 (.0196 .003) ref 8 9 10 7 6 3.00 0.102 (.118 .004) (note 3) 3.00 0.102 (.118 .004) (note 4) note: 1. dimensions in millimeter/(inch) 2. drawing not to scale 3. dimension does not include mold flash, protrusions or gate burrs. mold flash, protrusions or gate burrs shall not exceed 0.152mm (.006") per side 4. dimension does not include interlead flash or protrusions. interlead flash or protrusions shall not exceed 0.152mm (.006") per side 5. lead coplanarity (bottom of leads after forming) shall be 0.102mm (.004") max 0.254 (.010) 0 C 6 typ detail a detail a gauge plane 5.23 (.206) min 3.20 C 3.45 (.126 C .136) 0.889 0.127 (.035 .005) recommended solder pad layout 0.305 0.038 (.0120 .0015) typ 0.50 (.0197) bsc 0.1016 0.0508 (.004 .002) ms package 10-lead plastic msop (reference ltc dwg # 05-08-1661 rev e)
lt4351 20 4351fb linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax: (408) 434-0507 www.linear.com ? linear technology corporation 2003 lt 0609 rev b ? printed in usa related parts typical application part number description comments ltc4352 ideal diode controller with monitor controls n-channel mosfet, 0v to 18v operation ltc4354 negative voltage diode-or controller and monitor controls two n-channel mosfets, 1s turn-off, 80v operation ltc4355 positive voltage diode-or controller and monitor controls two n-channel mosfets, 0.5s turn-off, 80v operation ltc4357 positive high voltage ideal diode controller controls single n-channel mosfet, 0.5s turn-off, 80v operation ltc4358 5a ideal diode integrated n-channel mosfet, 0.5s turn-off, 9v to 26.5v ltc4412 low loss powerpath controller in thinsot? p-channel mosfet, 3v to 28v range thinsot is a trademark of linear technology corporation. gate out v in uv ov 1f mbr0530 mbr0530 r1 1.07k 1% 10h 12.6v battery1 charger lt4351 sw v dd status 5 fault gnd si4408dy 3 1 1 7 6 4 2 110 9 8 r2 40.1k 1% 0.1f 10f 100f uv fault = 11.8v 10f 10k 5% 10k 5% out 100k 5% 10f + gate out v in uv ov 1f mbr0530 mbr0530 300k 5% 10h 1n914 12.6v battery2 charger lt4351 sw v dd status 5 fault gnd power is switched to battery2 when battery1 drops to 11.8v si4408dy 3 7 6 4 2 110 9 8 120k 5% 10f 0.1f 10f 10f 10k 4351ta04 out 100f 10k load + + 100f + primary battery with secondary battery backup

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